Testing Software - C-LINK
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C-LINK DTM – Design To Manufacturing

Electronics manufacturers are challenged by continuous innovation, everincreasing global competition and price pressure, and the need to coordinate design and manufacturing centers at different locations.

C-LINK helps them to be more competitive by bridging the gap between Design and Manufacturing to achieve faster time to build, time to market and time to volume, cost reductions and higher quality. It is a modular, scaleable integrated solution for any electronics circuit board manufacturer, small, medium or large.

C-LINK DTM gives manufacturing personnel at any location full visibility to all design data, making it possible both for in-house design and manufacturing units and for Original Electronics Manufacturers (OEMs) and Contract Electronics Manufacturers (CEM's) to cooperate effectively. Cross-functional teams can audit design data and prepare manufacturing data for checking in order to eliminate errors before investment in bare board fabrication and production. Engineering Change Orders (ECO's) can be executed at manufacturing centers.

    
C-LINK DTM
's compact, complete manufacturing database contains all product build data in a normalized format for exploitation at all stages in the manufacturing process. It includes printed circuit board (PCB) layout data from computer aided design (CAD) systems, circuit schematics data from computer aided engineering (CAE) systems and bill of materials (BOM) data. Relationships between CAD, in-house and machine vendor part numbers and packages are managed by links to part numbers from approved vendors in C-LINK DTM 's Component Database (CDB). The CDB is prefilled with 36,000 electrical models and 1,000 package models.All manufacturing data can be quickly transferred via secure Internet transmission to the best manufacturing locations.

  
C-LINK DTM
's concurrent engineering automation solutions eliminate bottlenecks in the manufacturing process, speeding up total time from the end of PCB layout to finished boards by a factor of 3 to 5 when compared to traditional methods. Assembly line optimization reduces cycle and feeder changeover times. Test optimization automates mechanical fixture design/redesign and balances test between boundary scan test systems and in-circuit or flying probe test systems, reducing fixture costs and test time. ROI (Return On Investment) on a typical C-LINK configuration is after processing 5 to 8 boards. The more complex the boards, the faster the ROI.

C-LINK QMAN – Quality MANagement
C-LINK QMAN
automatically imports failure information, facilitates overall process control by generating real time trend alarms to arrest the production of faulty boards and enables fast paperless failure diagnosis and repair. In addition it feeds back quality information so that manufacturing managers can fix the overall process and achieve higher quality.All quality data is fully accessible in standard and customized reports.

C-LINK global solution
for board audit, assembly, test and quality
C-LINK workflow
C-LINK DTM
automatically recovers design data and increases return on assets by exploiting this data to speed up and improve the quality of every step in the manufacturing process.

Design visibility and validation
Preprocessors for all leading CAE and PCB Layout CAD systems automatically recover complete and intelligent design data. The BOM converter wizard automatically recovers bills of materials in any format. Full graphical visibility to design and added manufacturing data, coupled with automated manufacturability and testability checks, speed up design audits and feedback to designers. ECO's (add/delete component, cut net, add wire) can be carried out directly without board redesign.

  
Production preparation
C-LINK DTM supports panelisation of single or heterogeneous boards. Powerful surface mount line optimization algorithms minimize feeder changeover times and minimize cycle time. Assembly machine postprocessors automatically generate optimized programs for surface mount and through hole assembly systems. Assembly documentation shows the components assigned to each machine and to manual insertion.


Test preparation
C-LINK DTM carries out physical adaptability/ contact ability and board testability checking with respect to comprehensive rules. It balances components between boundary scan and in-circuit or flying probe testers. It supports full single and double sided mechanical test fixture design (and redesign) including graphical display of all plates (top, bottom and ground) and placement of all mechanical items and cut outs. It automatically generates test fixture drill files, wiring lists, and input lists for all leading in circuit, flying probe and boundary scan testers. Specific features and constraints of target testers are fully taken into account. Cross-linked intelligent PCB layout and circuit schematics graphics with full tester pin back annotation acerbate diagnosis and debugging.

  Quality management
C-LINK QMAN automatically recovers failure data logged by test systems, monitors repeated failures and generates real-time trend alarms so that production of faulty boards can be stopped. Diagnosis and repair are guided by a fault catalog based on past history and by the graphical display of failure locations on hot-linked board layout and circuit schematics. Comprehensive reports filtered by top occurrences and percentage threshold are extracted from the QMAN database to ensure that process steps that generate failures are fixed.


C-LINK DTM concurrent engineering
eliminates manufacturing bottlenecks
The chart above shows the traditional linear engineering schedule for manufacturing a typical surface mount board starting with PCB Layout and ending with the completion of Test Program Debug. Production Preparation can take up to 3 weeks and Test Preparation up to 6.5 weeks.
Using this approach, boards are fabricated before Production Preparation and Test Preparation and so any design problems are detected too late during production or during test. Time from the end of PCB Layout to the end of Test Program Debug is up to 17 weeks. The second chart shows the concurrent engineering schedule using C-LINK .

 
One day is added to PCB Layout to carry out the board audit on C-LINK and fix design problems and make improvements on the PCB Layout system. Production Preparation and Test Preparation each take 3 hours. With C-LINK you can do in an hour what used to be done in a week or more. Test Program Debug time is reduced because there are fewer errors in the circuit description and debug is assisted by the graphical display of crosslinked intelligent board layout and circuit schematic graphics. Time from the start of the additional Board Audit step to the end of Test Program Debug is just over 4 weeks, 4 times faster than the traditional engineering schedule.

 
C-LINK DTM and QMAN software solutions
modular, integrated and scalable for all typical applications
Test Stations automate test data preparation and eliminate bottlenecks. They manage the whole process from intelligent graphical design data input through library management, net adaptability checking, component testability checking and full mechanical fixture design to the generation of input lists and circuit description files for all leading in-circuit, flying probe and boundary scan testers. A customizable generic postprocessor is also available. Test personnel located at any manufacturing location have full visibility to design data. Comprehensive design for testability checks mean that any problems can be quickly identified and either fed back to design for correction or corrected directly on the Test Station, before investment in board fabrication and production. Test balancing between boundary scan testers and in circuit or flying probe testers reduced fixture costs and shortens test time. Tester specific features and constraints are fully taken into account including analog ICT, digital ICT, logic per pin, logic per group, logic families, Opens Check, TestJet, Opens Express, FrameScan, 4-wire (Kelvin) measurement, net testing strategy support for flying probe testers.There is full support for single and double sided mechanical test fixture design (including capacitive probes, support blocks, push downs, tooling pins and other mechanical items). 100% accurate drill file output (for each fixture layer) and wiring list output means that fixtures can be built right the first time, eliminating expensive hardware changes. Consistency between the C-LINK database and the tester is assured by back annotation of nail numbers allocated by multiplexed testers and of changes made by the fixture manufacturer or during debugging. In addition, integrated fixture redesign functionality minimizes the time and cost of fixture maintenance for different board revisions. Automatic back annotation of tester pin numbers to the circuit schematics coupled with hot-linked intelligent PCB layout and circuit schematics graphics (so that components, nets, nails, etc. selected in the layout are automatically highlighted in the schematics and vice-versa), significantly speeds up problem diagnosis and test program debugging.


The Production Station includes high performance, easily configured, practical assembly optimization for surface mount assembly lines using three different strategies. In addition to providing significant gains on high mix lines, the optimizer carries out feeder pool management. Assembly documentation shows components to be mounted by each machine/station. Machine programs are generated automatically and a customizable generic postprocessor is available. Forthcoming features include common feeder setups for multiple boards with fixed and flexible feeder support, feeder setup verification, assembly program verification (highlighting differences between design and machine program component centers and rotations), back annotation from machine programs to C-LINK database, batch optimization on different lines, and line specific reports.

The C-LINK Component Database (CDB) Library contains all component information required for test fixture design/probe selection and for generating optimized programs for production and test machines/systems. It is pre-filled with 36,000 electrical models and 1,000 package models and more than 1,000 data sheets in PDF format that are linked to these models. Part numbers from approved vendors are associated with these electrical and physical models. It is easy to add new models to the database and to associate data sheets with them. The database benefits from highly sophisticated import/export capabilities via ODBC and SQL and can be customized to support new tables for assembly and test machines. All C-LINK stations access component data stored in the CDB. A Contract Electronic Manufacturer (CEM) can maintain different CDB's for different customers, streamlining the processing of customer jobs.

The Board Input/Control Station makes it possible for manufacturing personnel to ensure design integrity, update design data and execute ECO's (Engineering Change Orders) before fabrication and production. Automatic DFM (Design for Manufacturing) checks include distance checks (pin to pad, component to component, component to board outline), via inside SMD pad, tooling hole covered by component, solder mask clearance for SMD components, existence of board reference markers, distance between reference markers and board outline and component outlines. Automatic DFT (Design for Test) checks establish whether or not nets on the board are accessible for test. Rules include minimum test pad size, distance checks (test pad to real component outline, board outline, drills, cut-outs etc., test pad to test pad). Electrical values for 4-wire measurements (Kelvin) and complex keep-out areas are taken into account. The DFT checks also determine whether or not a single or double sided fixture is required, and identify single pin nets. Reports list all accessible test pads, all inaccessible nets and affected components and pins (with reason for inaccessibility). Hot-links between the reports and board layout and circuit schematics display the nets concerned graphically. In addition there is a full set of features for updating design data for manufacturing including: change net names, edit part numbers, define board versions, define/shift probe locations on component pads or lands, edit board outline, edit component outlines, add documentation (text, drawings, symbols). ECO's (Engineering Change Orders) including cutting nets, adding wires, and adding or deleting components can be executed without having to go back to design. Other features include panelization of single or heterogeneous boards at any rotation and standard and user-defined reports. Applicable Board Input/Control Station functionality is included in Test and Production Stations.

The intelligent PCB layout and circuit schematic View Station provides graphical support for board validation, test, assembly, debugging and failure diagnosis/repair. It is included in all other C-LINK Stations and in C-LINK QMAN . Selected features are as follows. View/search/highlight design data including components, parts, nets and their properties. View/search/highlight multi-page schematics via nets and components table. View synthesis of all components and pins connected to a specified net on a separate schematics page. View manufacturing data (tester pins, ECO's, documentation, etc.) that has been added on a C-LINK Input/Control, Test or Production station. Standard and user-defined views for all manufacturing tasks. View cluster test components. Color coded test coverage graphics (green = fully tested, orange = partially tested, red = not tested). Test strategy graphics (components tested by ICT, AOI or FT). View fault locations and most frequent fault location. Generate standard and user-defined Reports. Hotlinks between list/message items and graphics. An independent intelligent Circuit Schematics importer and viewer is also available.

C-LINK QMAN automatically imports failure data logged by Automatic Test Equipment (ATE) and Automatic Optical Inspection (AOI) Systems, using configurable rules. Failure data is automatically monitored for repeated failures specified by the user. Repeated failures trigger automatic trend alarms which are dispatched electronically to manufacturing mangers and supervisors. Incoming failure data is stored in QMAN's active database (SQL Server) for recovery by paperless graphical Repair Stations which automatically locate failures graphically on cross-linked board layout and circuit schematics and display a fault catalog that identifies the most probable cause of failure. Quality engineers can diagnose the causes and producers of failures and enter repair actions to be taken independently by repair operators. All failure types, causes, producers and possible repair actions can be specified by the Quality Management System administrator. Depending upon the number of failures processed, failure information is archived to one or more archive databases. Report Stations generate standard and custom quality reports extracted from QMAN's active and archive databases, showing most common causes and producers of failures, etc., to ensure that upstream processes are fixed and improved.

 

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